Cache 6-11
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
• A memory write that occurs after a previous cache up-
date to the same location is a writeback. Writebacks are
driven as burst cycles on the bus.
■ Coherency State—There is a relationship between MESI
coherency states and writethrough-writeback coherency
states of lines in the cache:
• shared MESI lines are in the writethrough state
• modified and exclusive MESI lines are in the writeback
state
Table 2-2 on page 2-19 gives an overview of cache-access states
from the viewpoint of both memory writes and coherency
state. Chapter 5 deals with memory writes. This section deals
with the coherency state of cache lines.
Typically, system logic participates in the coherency control of
individual data-cache lines during read misses and write hits to
shared lines by driving WB/WT as shown in Tables 5-17 and 5-18
on page 5-135. The PWT bit also enters into this control, but it
is written by the operating system rather than system logic.
Alternatively, system logic can force the on-chip data cache to
statically observe a writethrough or a writeback protocol by
tying WB/WT as follows:
■ Writethrough Protocol—Tie WB/WT Low
■ Writeback Protocol—Tie WB/WT High
In the writethrough protocol, a cache line is either in the
shared or invalid state. All write hits to shared lines in the data
cache also cause 1-to-8-byte writethroughs to memory. Thus, in
writethrough cache lines, the MESI protocol is not fully
observed—the line never transitions to the exclusive or modi-
fied MESI states. In the writeback protocol, by contrast, a
cache line can be in the shared, exclusive, modified, or invalid
MESI state. Write hits only cause writethroughs to memory if
the hit is to a shared line. Writebacks can be caused by inquire
cycles, internal snoops, the FLUSH signal, the WBINVD
instruction, or cache-line replacements.
The advantages and disadvantages of these modes are as fol-
lows:
■ Writethrough Protocol:
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