6-32 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
tion 6.3.6. The SMM service routine should test bit 1 of the I/O
trap dword to determine the validity of the I/O instruction
before writing the I/O trap restart slot. If the I/O instruction
was valid, the SMM service routine can safely rewrite the I/O
trap restart slot with the value 00FFh, which causes the proces-
sor to re-execute the trapped I/O instruction when the RSM
instruction is executed. If the I/O instruction was invalid, writ-
ing the I/O trap restart slot has undefined results. If sequential
SMI interrupts occur, the second entry into SMM will never
have bit 1 of the I/O trap dword set, and the second SMM ser-
vice routine should not rewrite the I/O trap restart slot.
The pseudo-code for implementing I/O Trap Restart in BIOS is
as follows:
begin
{
if I/O instruction needs to be restarted then
{
if valid I/O instruction (test offset FFA4) then
set I/O restart slot (offset FF00) to 00FFh
}
}
end
During a simultaneous SMI I/O-instruction trap and debug
breakpoint trap, the AMD-K5 processor first responds to the
SMI and postpones writing the exception-related information
to the stack until after the return from SMM via the RSM
instruction. If debug registers DR3–DR0 are used in SMM, they
must be saved and restored by the SMM software. The proces-
sor automatically saves and restores DR7–DR6. If the I/O trap
restart slot in the SMM state-save area is written with the
value 00FFh when the RSM instruction is executed, the debug
trap does not occur until after the I/O instruction is re-exe-
cuted.
6.3.8 Exceptions and Interrupts in SMM
When SMM is entered, the processor disables both INTR and
NMI interrupts. On both the AMD-K5 and Pentium processors,
INTR interrupts are disabled by clearing the IF flag in
EFLAGS. But the mechanism by which NMI interrupts are dis-
abled and subsequently recognized differs between the
AMD-K5 and Pentium processors.
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