AMD K5 User Manual

Control Register 4 (CR4) Extensions 3-7
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Figure 3-1 and Table 3-1 show the fields in CR4. Figure 3-4 and
Table 3-2 show the fields in a page-directory entry.
4-Kbyte page translation differs from 4-Mbyte page translation
in the following ways:
■ 4-Kbyte Paging (Figure 3-2)—Bits 31–22 of the linear address
select an entry in a 4-Kbyte page directory in memory,
whose physical base address is stored in CR3. Bits 21–12 of
the linear address select an entry in a 4-Kbyte page table in
memory, whose physical base address is specified by bits
31–22 of the page-directory entry. Bits 11–0 of the linear
address select a byte in a 4-Kbyte page, whose physical base
address is specified by the page-table entry.
■ 4-Mbyte Paging (Figure 3-3)—Bits 31–22 of the linear
address select an entry in a 4-Mbyte page directory in mem-
ory, whose physical base address is stored in CR3. Bits 21–0
of the linear address select a byte in a 4-Mbyte page in
memory, whose physical base address is specified by bits
31–22 of the page-directory entry. Bits 21–12 of the page-
directory entry must be cleared to 0.
Figure 3-4. Page-Directory Entry (PDE)
Available to Software AVL 11–9
Global G 8
Page Size PS 7
Dirty = 0 D 6
Accessed A 5
Page Cache Disable PCD 4
Page Writethrough PWT 3
User/Supervisor U/S 2
Write/Read W/R 1
Present (valid) P 0
876543210
31
P
C
D
U
/
S
W
/
R
G
9101112
A
V
L
P
S
A
P
W
T
P
Physical Base Address
0

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm