AMD K5 User Manual

5-1
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5
Bus Interface
This chapter describes two closely related subjects, bus signals
(Sections 5.1 and 5.2) and the bus-cycle protocols implemented
with those signals (Sections 5.3 and 5.4). These sections
describe only the architectural characteristics and functions of
the signals and bus cycles. The processor data sheet defines
the setup and hold times for signals.
Throughout this chapter, unless otherwise stated, the term
clock refers to bus-clock (CLK) cycles, not processor-clock
cycles. The term cycle refers to bus cycles not clock cycles. The
terms asserted and negated mean that a signal is sampled
asserted or sampled negated by its target on the signal’s active
(typically rising) clock edge.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm