Signal Descriptions 5-109
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.45 RESET (Reset)
Input
Summary The assertion of RESET initializes the processor to the power-
up state.
Sampled The processor samples RESET every clock and recognizes it at
the next instruction boundary. The RESET process begins at
the falling edge of RESET. To be recognized, RESET must be
held asserted for at least 1 ms after V
CC
and CLK reach specifi-
cation.
The following inputs are sampled on the falling edge of
RESET:
■ BF (BF1–BF0) is(are) sampled to select the frequency ratio
between the processor’s internal clock and the bus clock
(CLK).
■ If FLUSH is asserted, the processor invokes the three-state
(float) test.
■ If FRCMC is asserted, the processor enters Functional-
Redundancy Checking mode as the checker.
■ If INIT is asserted, the processor performs its built-in self
test (BIST) before initialization and code fetching begin.
The processor samples RESET at all times, except in the Stop
Clock state and while INIT or PRDY is asserted. System logic
can drive the signal either synchronously or asynchronously
(see the data sheet for synchronously driven setup and hold
times).
Details RESET is typically asserted at power-up by a power-good sig-
nal from the power supply, which is turned on by a hardware
switch. RESET can also be asserted after power-up. For exam-
ple, pressing a front-panel button can cause a BIOS interrupt to
write to an I/O port (such as port 64h in the keyboard control-
ler). After RESET, the operating system usually determines
the cause of the reset (reset during or after power-up) with
another BIOS interrupt that queries another I/O port (such as
location 0Fh in the CMOS memory at ports 70 and 71h), and it
uses this information to determine whether a full power-on test
(POST) of the system should be run.
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