5-156 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.4.4 Bus Arbitration and Inquire Cycles
The processor bus may be required by another bus master,
which may need to drive its own cycles on the bus, or by system
logic, which may need to drive an inquire cycle to the proces-
sor or resolve bus deadlock. One of three signals can be used
for these purposes: AHOLD, BOFF, or HOLD. AHOLD’s sole
function is to support inquire cycles. It obtains control only of
the address bus and allows another master or system logic to
drive only inquire cycles, whereas BOFF and HOLD obtain
control of the full bus (address and data), allowing another
master to drive not only inquire cycles but also read and write
cycles. BOFF provides the fastest access to the bus and it
aborts any in-progress cycle by the processor. AHOLD and
HOLD both permit an in-progress bus cycle to complete, but a
writeback can occur while AHOLD is asserted whereas a pend-
ing writeback during the assertion of BOFF or HOLD occurs
after the BOFF or HOLD is negated.
In most systems, the choices are between BOFF and AHOLD.
Due to its slow response time, HOLD is usually considered only
when backward-compatibility with prior-generation sub-
systems requires it or when the integrity of in-progress bus
cycles is of paramount importance. Support for BOFF is usu-
ally needed to resolve potential deadlock problems that arise
as a result of inquire cycles, and if BOFF is supported, there is
usually no reason to support HOLD. The sections that follow
further describe these relative advantages and disadvantages.
In systems with multiple caching masters and shared memory,
system logic can maintain cache coherency by driving inquire
cycles to the processor whenever another bus master accesses
shared memory. Such system-initiated bus cycles cause the
processor to compare the physical tags for both its instruction
and data caches with the inquire address, in parallel with any
cache accesses the processor makes via its linear tags. If a
match is found, the processor writes the cache line back to
memory, if modified, and changes the MESI state according to
the state of the INV input signal during the inquire cycle.
The system logic’s sequence for driving inquire cycles is:
1. Assert AHOLD to obtain control of the address bus, or
assert either BOFF or HOLD to obtain control of the entire
bus.
To Next Page
Loading...
Need help?
General
