5-114 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.46 SCYC (Split Cycle)
Output
Summary The processor asserts SCYC during misaligned, locked trans-
fers on the D63–D0 data bus. The processor generates addi-
tional bus cycles to complete the transfer of misaligned data.
Driven and Floated The processor drives SCYC from the clock in which ADS is
asserted until the last expected BRDY of the bus cycle.
SCYC may be driven during any memory and I/O cycles,
whether locked or not, but it is only meaningful during locked
memory cycles in the normal operating modes (Real, Pro-
tected, and Virtual-8086) and in SMM. SCYC is not driven or is
not meaningful during unlocked memory cycles, I/O cycles,
inquire cycles, special bus cycles, or interrupt acknowledge
operations; in the Shutdown, Halt, Stop Grant, or Stop Clock
states; while BOFF, HLDA, RESET, or INIT is asserted; or
while PRDY is asserted. While AHOLD is asserted, SCYC is
driven only to complete a locked memory cycle already begun
before the assertion of AHOLD.
The processor floats SCYC one clock after system logic asserts
BOFF and in the same clock that the processor asserts HLDA.
Details For purposes of bus cycles, the term aligned means:
■ 2- and 4-byte transfers lie within 4-byte address boundaries
■ 8-byte transfers lie within 8-byte address boundaries
(For purposes of exceptions, the term aligned means situated
on the natural boundaries of an instruction or operand. Thus, a
2-byte transfer that crosses a 2-byte address boundary may
incur an alignment exception, but it will be performed as an
aligned bus cycle.)
If data on D63–D0 is misaligned, the processor generates addi-
tional bus cycles to complete the transfer. For example, if a 4-
byte transfer begins at address x07h, one byte is transferred
during the first bus cycle and the remaining three bytes are
transferred during a second bus cycle, which normally occurs
immediately after the first bus cycle (unless intervened, such
as by an interrupt or bus backoff). If the misaligned transfer is
run as a locked cycle, the processor asserts both LOCK and
SCYC throughout the misaligned sequence of bus cycles.
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