6-22 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
6.2.7 Cache Invalidations
The term invalidation usually means one of the following
things:
■ Individual Cache Lines—Writebacks and/or invalidations of
single lines in the instruction and data caches can be done
with inquire cycles (driven by system logic) or internal
snoops (initiated by the processor). These invalidations are
described in Section 6.2.4 on page 6-12, in the section on
Internal Snooping on page 2-22, and elsewhere throughout
this manual.
■ Entire Cache Contents—Writebacks and/or invalidations of
the entire contents of the instruction and data caches can
be done with the INVD or WBINVD instructions, or with the
FLUSH signal. These invalidations are typically performed
by the operating system or system logic during task or mode
changes. The invalidations are described on pages 5-65 and
5-180.
The MESI-state transitions for cache invalidations are given in
Table 2-3 on page 2-20.
6.2.8 A20M Masking of Cache Accesses
The processor samples A20M only in Real mode, and applies
A20M masking to its linear cache tags, through which all pro-
grams access the caches. Thus, assertion of A20M affects all
program-generated cache addresses, including the following:
■ Cache-line fills (caused by read misses)
■ Cache writethroughs (caused by write misses or write hits
to lines in the shared state)
■ Cache accesses that occur while the processor does not con-
trol the bus
However, A20M does not mask writebacks or invalidations
caused by the following actions, which are looked up only in
the physical (not the linear) tags:
■ Internal snoops
■ Inquire cycle
■ The FLUSH signal
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