AMD K5 User Manual

Signal Descriptions 5-127
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.50 TCK (Test Clock)
Input
Summary TCK is the clock for boundary-scan testing using the Test
Access Port (TAP).
Sampled The processor always samples TCK, except while RESET or
INIT is asserted. The signal has an internal pullup resistor.
Details Data and state definition are clocked into the processor on the
rising edge of TCK. The outputs on TDO are driven valid on the
falling edge of TCK. When TCK stops on its falling edge, the
state of test latches in the processor are held.
Section 7.8 on page 7-19 summarizes the implementation of
TAP testing on the AMD-K5 processor. System logic should tie
TCK High if TAP testing is not implemented.
See the IEEE Standard Test Access Port and Boundary-Scan
Architecture (IEEE 1149.1) specification for details on how the
TAP signals and instructions are used for testing. The TAP is
often called the Joint Test Action Group (JTAG) port, after the
committee that proposed the IEEE TAP standard.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm