7-6 Test and Debug
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
LFSR signature test on the PLA, in that order. Upon comple-
tion of the PLA test, the processor transfers the test result
from an internal Hardware Debug Test (HDT) data register to
the EAX register for external access, resets the internal micro-
code, and begins normal code fetching.
The result of the BIST can be accessed by reading the lower 9
bits of the EAX register. If the EAX register value is
0000_0000h, the test completed successfully. If the value is not
zero, the non-zero bits indicate where the failure occurred, as
shown in Table 7-2. The processor continues with its normal
boot process after the BIST completes, whether the BIST
passed or failed.
7.2.2 Test Access Port (TAP) BIST
The TAP BIST performs all of the functions of the normal
BIST, up to and including the PLA signature test, in the exact
manner as the normal BIST. However, after the PLA test, the
test result is not transferred to the EAX register.
The TAP BIST is started by loading and executing the RUN-
BIST instruction in the test access port, as described in Section
7.8 on page 7-19. When the RUNBIST instruction is executed,
the processor enters into a reset mode that is identical to that
entered when the RESET signal is asserted. Upon completion
Table 7-2. BIST Error Bit Definition in EAX Register
Bit Number
Bit Value
01
31–9 No Error Always 0
8 No Error Data path
7 No Error Instruction-cache instructions
6 No Error Instruction-cache linear tags
5 No Error Data-cache linear tags
4 No Error PLA
3 No Error Microcode ROM
2 No Error Data-cache data
1 No Error Instruction cache physical tags
0 No Error Data-cache physical tags
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