AMD K5

Cache and TLB Testing 7-15
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Figure 7-8. Test Formats: 4-Mbyte TLB
EDX: Array Pointer
031 30 29 28 27
0 0
Array ID
(EAh, EBh)
Entry
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EAX: Test Data
(EAh) 4-Mbyte Page and Status
(EBh) 4-Mbyte Linear Tag
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Valid Bits
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Valid Bits
87
31
0111231
1415