AMD K5 User Manual

Bus Cycle Timing 5-153
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Burst Writeback Figure 5-8 shows a burst read followed by a writeback. Write-
backs are the only type of burst write that the processor per-
forms. They can be initiated by the processor or by system
logic in the following cases:
■ Processor-Initiated Writebacks:
• Replacement—If a cache-line fill is initiated when all
four ways of the cache that could accommodate the in-
coming line are filled with valid entries, the processor
uses a round-robin algorithm to select a line for replace-
ment. Before a replacement is made to a data cache line
in the modified state, the line is written back to memory.
• Internal Snoop—The processor snoops the data cache
whenever an instruction-cache line is read, and it snoops
the instruction cache whenever a data cache line is writ-
ten. This snooping is performed to determine whether
the same address is stored in both caches, a situation
that is taken to imply the occurrence of self-modifying
code. If a snoop hits a data cache line in the modified
state, the line is written back to memory before being in-
validated.
• WBINVD Instruction—When the processor executes a
WBINVD instruction, it writes back all modified lines in
the data cache and then invalidates all lines in both
caches. The action taken in response to the WBINVD in-
struction is essentially the same as the action taken in
response to the FLUSH input signal, except that the ac-
knowledge cycles differ. For details, see page 5-185.
■ System-Initiated Writebacks:
• Inquire Cycle Hits—If an inquire cycle hits a modified
line in the data cache, the processor writes back the line.
For details, see page 5-157.
• FLUSH—If system logic asserts the FLUSH input, the
entire contents of the data cache are written back to
memory before the entire contents of both caches are in-
validated. The action taken in response to the FLUSH
input signal is essentially the same as the action taken in
response to the WBINVD instruction, except that the ac-
knowledge cycles differ. For details, see page 5-183.
During all processor-initiated and system-initiated FLUSH
writebacks, the processor asserts ADS, drives a 32-byte-aligned
starting address on A31–A3, and enables all eight bytes

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm