5-154 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
(BE7–BE0 = 00h). Thus, A4–A3 are always 0 for writebacks.
During inquire cycle writebacks, the processor does the same
thing, except that if system logic holds AHOLD asserted
throughout the writeback, the processor lets system logic pro-
vide the address.
The writeback shown in Figure 5-8 is caused by a cache-line
replacement, which occurs when an attempted burst read finds
that all four cache ways for that address are filled with valid
entries. In this case, the processor performs the following
sequence:
1. Copies the prior contents of the replacement line to its 32-
byte writeback buffer (described in Section 2.3.7 on page 2-
23). This is not visible on the bus.
2. Completes the burst read, placing the incoming data into
the cache line. This is the first burst cycle in Figure 5-8.
3. Writes the modified line back to memory. This is the second
burst cycle in Figure 5-8.
During the burst read (Step 2), the states of PWT and WB/WT
are the same as in Figure 5-6 and Figure 5-7.
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