AMD K5 User Manual

5-8 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
Table 5-2. Conditions for Driving and Sampling Signals
Signal
Conditions under which signals are meaningfully driven or sampled
Bus Cycles or Cache Accesses
38
Arbitration
States and Modes
8
Reset,
Debug
Memory Reads
14
Memory Writes
14
Cache Hits
39
Inquire Cycles
3
I/O Cycles Locked Cycles Special Cycles Interrupt Acknow. AHOLD Active BOFF Active HLDA Active Shutdown
33
Halt Stop Grant Stop Clock SMIACT Active RESET Active INIT Active PRDY Active
Bus Arbitration
AHOLD I
23 —
BOFF I —
BREQ O 38
HLDA O 39 35 —
HOLD I 35
Address and Address Parity
A20M
I 10 10 10 10 10 10 10 10 10
A31–A3
2
I/O 44 19 19 7 4 4 3 3 3
AP I/O 38 7 4 4 3 3 3
ADS O 38 37 3 3 3 3
ADSC O 38 37 3 3 3 3
APCHK O 7 3 3 3 3 3 3 3 3
BE7
–BE0 38 37 16 3 3 3
Cycle Definition and Control
D/C
O 38 37 16 3 3 3
EWBE I 37 26 26 3 3 3
LOCK O 38 1 — 16
M/IO O 38 37 16 3 3 3
NA
18
I 18 18 18 16 18
SCYC O 13 13 13
13 13
W/R
O 38 37 16 3 3 3

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm