AMD K5 User Manual

5-88 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.33 INV (Invalidate Cache Line)
Input
Summary During an inquire cycle, the state of INV determines whether
the addressed cache line, if found in the processor’s instruction
or data cache, transitions to the invalid or shared state.
Sampled INV is sampled with the same timing as EADS. See the descrip-
tion of EADS on page 5-58.
Details If INV is asserted when EADS is asserted at the beginning of
an inquire cycle, the processor transitions the line (if found) to
the invalid state, regardless of the state in which the cache line
was found; such cycles are sometimes called invalidate cycles,
or simply invalidations. If INV is negated when EADS is
asserted, the processor transitions the line (if found) to the
shared state. In either case, if the line is found in the modified
state, the processor writes it back to memory before changing
its state.
INV is typically asserted during a write by another caching
master. In such cases, INV can be generated by watching W/R
from another bus master and asserting INV to the processor,
along with EADS, only on writes. This method invalidates a
copy that the processor may have cached, whether modified or
not, for the same location being written by the other bus mas-
ter. The processor’s assertion of HITM and/or HIT does not
influence how INV affects a line found in the cache. Those two
outputs simply indicate whether the line was found (HIT) and
whether a writeback will follow (HITM). If INV is asserted dur-
ing the inquire, the resulting state of the line (invalid) is
entirely determined by INV, without reference to HITM and/or
HIT. If INV is negated during the inquire, the resulting state of
a hit line (shared) is also entirely determined by INV, but sys-
tem logic will not know whether a writeback is imminent with-
out monitoring HITM, and another bus master will not be able
to cache the line in the exclusive state without monitoring HIT.
For a comparison of the states that HITM, HIT, and INV can
assume, see Table 5-11 on page 5-71.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm