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5-184 Bus Interface

AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996

Cache-Invalidation

Cycle (INVD

Instruction)

Figure 5-23 shows the cache-invalidation special bus cycle,

which the processor drives in response to the execution of the

INVD instruction. The INVD instruction causes the processor

to invalidate each line in its instruction and data caches. Modi-

fied lines in the data cache are not written back.

Although the execution of INVD is not visible on the bus, the

lack of activity on the bus as the microcode invalidates the

lines in the internal cache can be seen. When all lines in both

caches are invalidated, the processor drives the cache-invalida-

tion special bus cycle (BE7–BE0 = FDh). System logic must

respond by asserting BRDY. When it does, the processor typi-

cally begins driving one or more burst reads on the bus to refill

its caches.

Figure 5-23. Cache-Invalidation Cycle (INVD Instruction)

CLK

A31–A3

ADS

BE7–BE0

BRDY

CACHE

D/C

D63–D0

KEN

LOCK

M/IO

W/R

CLK

INVD

Instruction

Completes

Cache Invalidation

Special Cycle

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