5-62 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.21 EWBE (External Write Buffer Empty)
Input
Summary The processor delays cache writes and certain serializing
instructions if system logic negates EWBE during external
writes.
Sampled The processor samples EWBE with the BRDY of external write
cycles and in every clock thereafter until EWBE is asserted.
Details All writes on the AMD-K5 processor—whether to cache, mem-
ory, or I/O—are performed in program order, regardless of the
state of EWBE. The only effect of EWBE on writes is to hold off
additional writes when the signal is negated.
The processor expects EWBE to be asserted with or after the
last BRDY of each write cycle. Thus for writebacks, the proces-
sor expects EWBE to be asserted with or after the BRDY of the
fourth transfer. System logic should assert EWBE when all
external write buffers are empty, thus indicating that the write
to memory or I/O has completed and that writes to the cache
can take place. Most systems tie EWBE Low (asserted), thus
allowing the speed of writes to be controlled only by BRDY.
If EWBE is sampled negated with the BRDY of an external
write cycle, the processor does not do any of the following:
■ Write store-buffer entry to data cache
■ Write to memory (single-transfer or burst), including locked
write to Accessed (A) bit after TLB load
■ Execute serializing instructions like MOV to CR0, MOV to
CR4, WBINVD, INVLPG, and CPUID:
■ Respond to the following interrupts:
• FLUSH
• SMI
■ Respond to any other interrupts or exceptions that cause a
write to memory, such as pushing state onto the stack or set-
ting the Accessed bit in a segment descriptor. This may
include the BUSCHK, NMI, and INTR interrupts.
For interrupts that do not write to memory (R/S, INIT, and
STPCLK), the state of EWBE has no effect on the processor’s
recognition of or response to such interrupts. The processor
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