Signal Descriptions 5-63
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
latches any edge-triggered interrupt that may not be recog-
nized while EWBE is negated (FLUSH, SMI, NMI) and recog-
nizes them in priority order when EWBE is asserted.
If system logic implements memory-mapped I/O as non-cache-
able memory (the standard method), EWBE on the AMD-K5
processor has the same effect on writes to memory-mapped I/O
as does EWBE on the Pentium processor—neither processor
reorders reads ahead of writes.
For more details on the function of EWBE, see the following
sections:
■ BRDY—Page 5-41.
■ HITM—Page 5-72.
■ SMI—Page 5-116.
■ SMIACT—Page 5-121.
■ STPCLK—Page 5-122.
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