AMD K5 User Manual

Boundary-Scan Test Access Port (TAP) 7-21
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
buffers to control and observe the behavior of signals at each
pin. The boundary scan cells form a serial shift-register chain,
called a Boundary Scan Register (BSR), around the processor’s
internal logic. Test data is shifted through the boundary-scan
chain by a test program. If all the components on a board
implement this boundary-scan architecture, a single serial
path can be used to test component interconnections.
Parallel output registers are fed by the shift registers. Parallel
data is loaded into the shift register when the TAP controller
exits the capture state (capture_DR or capture_IR). The shift
registers then shift data from TDI to TDO in the shift state
(shift_DR or shift_IR). The parallel output registers hold the
current data while new data is shifted into the shift registers.
The output registers are updated when the controller exits the
update state (update_DR or update_IR).
The sections below describe only those aspects of the IEEE
standard that are implemented uniquely by the AMD-K5 pro-
cessor. For a description of the IEEE-mandatory TAP functions
and the IEEE optional functions implemented by the AMD-K5
processor, see the IEEE Standard Test Access Port and Boundary-
Scan Architecture (IEEE 1149.1-1990) specification.
7.8.1 Device Identification Register
The format of the Device Identification Register (DIR) is
shown in Table 7-5. The fields include the following values:
■ Version Number—This is incremented by AMD manufactur-
ing for each major revision of silicon.
■ Bond Option—The two bits of the bond option depend on
how the part is bonded at the factory.
■ Part Number—This identifies the specific processor model.
■ Manufacturer—This is actually only 11 bits (11–1). The
least-significant bit, bit 0, is always set to 1, as specified by
the IEEE standard.
Table 7-5. Test Access Port (TAP) ID Code
Version
(Bits 31–28)
Bond Option
(Bits 27–26)
Part Number
(Bits 25–12)
Manufacturer
(Bits 11–0)
Xh XXb 05XXh 001h

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm