AMD K5

7-20 Test and Debug
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
The TAP consists of the following:
■ Test Access Port (TAP) Controller—A synchronous, finite
state machine that decodes the inputs on the TMS signal to
control a sequence of test operations.
■ Instruction Register (IR)—Accepts serially shifted instruc-
tions from the TDI input. The instructions select the test or
debug operation to be performed, the Test Data Register
(TDR) to be accessed, or both.
■ Test Data Registers (TDRs)—Used to process the test data.
Each TDR is addressed by an instruction in the Instruction
Register (IR). The processor includes the following TDRs:
• Boundary Scan Register (BSR)—Contains cells connected
to all of the processor’s input and output signals as well
as cells for I/O float control. It allows serial data to be
written into or read from the processor boundary. The
register is controlled with the EXTEST and SAMPLE in-
structions.
• Device Identification Register (DIR)—Contains the codes
for manufacturer's identification, part number, and ver-
sion.
• Bypass Register (BR)—A path between TDI and TDO
used to transfer test data to and from other board com-
ponents when no test operation is being performed by
the processor.
• Hardware Debug Tool Register (HDTR)—Selected by the
USEHDT instruction to connect TDI and TDO, allowing
HDT instructions to be executed.
• Built-In Self-Test Result Register (BISTRR)—Selected by
the RUNBIST instruction to connect TDI and TDO, al-
lowing the result of executing the RUNBIST to be
shifted out after the completion of BIST.
■ The test signals are as follows:
• TCK—The clock for all TAP testing
• TDI—Input test data and instructions
• TDO—Output data
• TMS—Test functions and sequence of test changes
• TRST—Test reset
Boundary-scan testing uses shift registers in boundary scan
cells located between the processor’s internal logic and I/O