6-28 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
6.3.3 SMM Revision Identifier
The SMM revision identifier at offset FEFCh in the SMM state-
save area specifies the version of SMM and the extensions that
are available on the processor. The SMM revision identifier
fields are as follows:
■ Bits 31–18—reserved
■ Bit 17—SMM base address relocation (always 1 = enabled)
■ Bit 16—I/O trap restart (always 1 = enabled)
■ Bits 15–0—SMM revision level = 0000
These fields are the same as in the Pentium processor. Unlike
the Pentium processor, however, the I/O trap restart and the
SMM base address relocation functions are always enabled in
the AMD-K5 processor and do not need to be specifically
enabled.
6.3.4 SMM Base Address
During RESET, the processor sets the code-segment (CS) base
address for the SMM memory area—the SMM Base Address—to
its default, 0003_0000h. The SMM base address at offset FEF8
in the SMM state-save area can be changed by the SMM ser-
vice routine to any address that is aligned to a 32-Kbyte bound-
ary. (Locations not aligned to a 32-Kbyte boundary cause the
processor to enter the Shutdown state when executing the
RSM instruction.)
FF04 I/O Restart EDI 32 read-only
FF02 Halt Restart Slot 16 (See Section 6.3.5) read/write
FF00 I/O Trap Restart Slot 16 (See Section 6.3.7) read/write
FEFC SMM Revision Identifier 32 (See Section 6.3.3) read-only
FEF8 SMM Base Address 32 (See Section 6.3.4) read/write
FE00–FEF4 reserved 32 —
Table 6-2. SMM State-Save Area Map (continued)
Offset (hex) Contents Size (bits) Type
Notes:
1. Locations marked “reserved” may change in future processors.
2. Writing locations marked as “read-only” has unpredictable results.
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