5-20 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.2 A31–A3 (Address Bus)
A31–A5 Bidirectional, A4–A3 Output
Summary A31–A3 carries the physical address for the current bus cycle.
The processor drives addresses on A31–A3 during memory and
I/O cycles, and cycle definition information during special bus
cycles. It samples addresses on A31–A5 during inquire cycles.
Driven, Sampled, and
Floated
As Outputs: The processor drives A31–A3 from the clock in
which ADS is asserted until the last expected BRDY of the bus
cycle. The processor also drives A31–A3 without ADS during
cache accesses. A31–A3 are driven during memory cycles
(including cache writethroughs and writebacks), I/O cycles,
inquire cycle writebacks, locked cycles, special bus cycles, and
interrupt acknowledge operations in the normal operating
modes (Real, Protected, and Virtual-8086) and in SMM, and
while PRDY is asserted. During special bus cycles and inter-
rupt acknowledge operations, the address signals simply sup-
port bus cycle definition; they do not provide an address.
The processor floats A31–A3 as outputs, one clock after system
logic asserts AHOLD or BOFF, and in the same clock that the
processor asserts HLDA.
As Inputs: While AHOLD, BOFF, or HLDA is asserted, the pro-
cessor samples A31–A5 in the same clock as EADS. A31–A5 are
sampled in this way during inquire cycles in the normal operat-
ing modes (Real, Protected, and Virtual-8086) and in SMM,
including during the Shutdown, Halt, and Stop Grant states,
and while PRDY is asserted. The A4–A3 signals are not inter-
preted as part of the inquire cycle address but must neverthe-
less be driven at valid 0 or 1 logic levels. The processor may
again drive A31–A3 in the next clock after system logic negates
AHOLD, BOFF, or HOLD.
A31–A3 are never driven or sampled in the Stop Clock state, or
while RESET or INIT is asserted.
Details During processor-initiated bus cycles, the processor drives
A31–A3 with ADS to define an eight-byte (quadword) starting
address in physical memory or I/O space. System logic inter-
prets these addresses in conjunction with the BE7–BE0 and
cycle definition (D/C, M/IO, and W/R) outputs, and with the
A20M input. The processor drives BE7–BE0 to define the valid-
ity of each of the eight bytes accessed by the quadword
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