Signal Descriptions 5-19
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
paging mechanism. The operating system writes page table
entries so as to map all pages required for the Virtual-8086
mode task to addresses below 1 Mbyte.
Unlike the Pentium processor, the AMD-K5 processor ignores
A20M in Protected mode, Virtual-8086 mode, and System Man-
agement Mode (SMM). The Pentium processor masks the A20
bit if A20M is asserted in Protected mode or Virtual-8086
mode, even though this behavior is undefined and may change
in future processors. The AMD-K5 processor simply ignores
A20M except when the processor runs in Real mode.
The AMD-K5 processor applies A20M masking to its linear
cache tags, through which all programs access the caches.
Thus, assertion of A20M affects all program-generated cache
addresses, including cache-line fills (caused by read misses),
cache writethroughs (caused by write misses or write hits to
lines in the shared state), and cache accesses that occur while
the processor does not control the bus. However, A20M does
not mask writebacks or invalidations caused by internal
snoops, inquire cycles, the FLUSH signal, or the WBINVD
instruction—such addresses are looked up only in the physical
tags, which are not masked by A20M. (See Table 2-3 on page 2-
20 for details.) By contrast, the Pentium processor applies
masking only to physical addresses. This difference of masking
linear vs. physical addresses is not visible to software because
linear and physical addresses are identical in Real mode.
However, the AMD-K5 processor’s A20M linear address mask-
ing can affect debug software differently than such masking on
the Pentium processor. With A20M asserted, the AMD-K5 pro-
cessor does breakpoint matching (debug-register comparisons)
on masked addresses, whereas the Pentium processor does
them on unmasked addresses.
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