AMD K5 User Manual

Execution Pipeline 2-7
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
2.2.2 Decode
The two-stage decode logic accepts predicted x86 instruction
bytes and their predecode bits from the fetch logic, shifts them
into a 16-byte FIFO buffer called the byte queue, merges regis-
ter tags and operands, and generates internal RISC operations
(ROPs). The decode logic also generates microcode entry
points for complex instructions, interrupts and exceptions, and
several other functions, and it manages the floating-point
stack.
ROPs are fixed-format internal instructions with up to three
operands. Most ROPs execute in a single clock. The operands
(up to two source and one destination) can be 1-, 2-, or 4-bytes
wide, or half of an 8- or 10-byte floating-point operand. ROPs
can be combined to perform every function of an x86 instruc-
tion. One x86 instruction can be decoded into as few as one
ROP (for example, a register-to-register add), or it can be
decoded into several ROPs, depending on its complexity.
The processor uses a combination of hardware and microcode
to convert x86 instructions into ROPs. The hardware consists
of four parallel fastpath converters that translate the most
commonly used x86 instructions (moves, shifts, branches,
ALUs) into one, two, or three ROPs. Translations requiring
more than three ROPs (complex instructions, serializing condi-
tions, interrupts and exceptions, etc.) are handled by micro-
code. Microcode generates the same types of ROPs as the
fastpath hardware but in streams longer than three. The prede-
code information stored with each x86 instruction byte speci-
fies the number of ROPs that instruction requires, or it
specifies that microcode is required. The decoder provides the
entry point into microcode for complex operations.
Pipeline serialization (or synchronization) is handled at the
decode stage. When the processor decodes a serializing instruc-
tion, it stops decoding at that instruction, waits for all previ-
ously decoded instructions to retire (described in Section 2.2.5
on page 2-12), then decodes and executes through retirement
the serializing instruction before decoding any additional
instructions. Thus, the serializing instruction is guaranteed to
execute in program order.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm