AMD K5 User Manual

3-2 Software Environment and Extensions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
The sections that follow provide details on the architectural
extensions visible to system and application software. Some
sections include pseudo-code algorithms for suggested BIOS
modifications to support the extensions. Architectural exten-
sions visible to debug and test software, such as I/O break-
points, are described in Chapter 7.
3.1 Control Register 4 (CR4) Extensions
Control register 4 contains bits that enable or specify many of
the extensions to the 486 architecture. The majority of the bits
in CR4 are reserved. The default state for all bits in CR4 is all
zeros. Figure 3-1 shows the format of CR4. Table 3-1 describes
the fields in CR4.
Figure 3-1. Control Register 4 (CR4)
Global Page Extension GPE 7
Machine Check Enable MCE 6
Page Size Extension PSE 4
Debugging Extensions DE 3
Time Stamp Disable TSD 2
Protected Virtual Interrupts PVI 1
Virtual-8086 Mode Extensions VME 0
7654321031
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Reserved
8

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm