AMD K5

6-36 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
Figure 6-6. Clock Control State Transitions
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HLT Instruction
Stop Grant
State
Normal Mode
- Real
- Virtual-8086
- Protected
- SMM
Halt
State
Stop Clock
State
RESET, SMI, INIT,
or INTR Asserted
Stop Grant
Inquire
State
STPCLK Asserted
STPCLK Negated,
or RESET Asserted
STPCLK Asserted
STPCLK Negated
CLK
Started
CLK
Stopped