Signal Descriptions 5-17
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
cache lines back to memory, an in-progress writeback will be
aborted, but it will be restarted after BOFF is negated, and the
FLUSH operation will then continue; any writebacks that com-
pleted before BOFF was asserted are not affected.
5.1.4 Bus Signal Compatibility with Pentium Processor
The differences in bus signal functions between the AMD-K5
and Pentium processors are described in Section A.1 on page
A-2.
5.2 Signal Descriptions
The following pages describe each signal in detail. The bus
cycle protocols that use these signals are described in Section
5.3 on page 5-136. Chapter 6 describes the context in which the
SMM and clock-control signals are used, and Chapter 7 does
the same for the test signals.
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