AMD K5

6-14 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
Inquire cycle logic in systems with look-aside caches can be
simplified by monitoring only HITM and ignoring HIT. This
works because the resulting state of a hit line is determined
only by the state of INV during the inquire as follows:
■ If INV is negated during a hit, the hit line—whether shared,
exclusive or modified—transitions to the shared state. Thus,
the inquiring master can safely cache the same data in the
shared state without knowing whether the inquire cycle hit
in the processor’s cache (and thus, without system logic
monitoring HIT).
■ If INV is asserted during a hit, the hit line—whether shared,
exclusive or modified—transitions to the invalid state. For
modified lines, the invalidation occurs after a writeback.
■ If the inquire cycle misses, irrespective of the state of INV,
the inquiring master can cache the target data in the shared
state, although it will not have enough information to cache
that line in the exclusive state (this requires that HIT be
monitored).
Lookaside caches must implement a signal with which to
inform the memory controller that a processor access or an
inquire cycle hit the L2 cache, so as to disable the memory
from responding. A version of HIT can be implemented for this
purpose.
Inquire cycle logic in systems with a look-through L2 cache
normally monitor both HIT and HITM from the processor,
because such systems often implement the write-once cache
protocol. This protocol requires caching in the exclusive state at
certain transitions, and the exclusive state can only be identi-
fied if both HIT and HITM are monitored.
6.2.5 Bus Arbitration for Inquire Cycles
Before running an inquire cycle, system logic must obtain con-
trol of the address bus by asserting AHOLD, BOFF, or HOLD.
These signals provide access to the bus with differing condi-
tions and speed.
In most systems, the choices are between BOFF and AHOLD.
Due to its slow response time, HOLD is usually considered only
when backward compatibility with prior-generation sub-
systems requires it or when the integrity of in-progress bus