AMD K5

Bus Cycle Timing 5-195
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
INIT-Initiated
Transition from
Protected Mode to
Real Mode
Figure 5-28 shows an example in which the operating system
writes to an I/O port, causing system logic to assert INIT. The
assertion of INIT starts an extended microcode sequence that
terminates with a code fetch from the Reset location.
INIT is typically asserted in response to a BIOS interrupt that
writes to an I/O port. This is often, for example, in response to
the operator’s pressing Control-Alt-Del. The BIOS writes to a
port (such as port 64h in the keyboard controller) that asserts
INIT. INIT is also used to support 286 software that must
return to Real mode after accessing extended memory in Pro-
tected mode. The 286 processor does not have an INIT input—
a transition from Protected mode to Real mode can only be
made on the 286 processor by asserting RESET. With the INIT
signal, however, the operating system can cause the transition
through a BIOS interrupt without loss of cache contents or
floating-point state.
Upon recognizing an INIT interrupt at the next instruction-
retirement boundary, the processor performs the following
actions, in the order shown:
1. Flush Pipeline—The processor invalidates the instruction
pipeline and TLB. This is not visible on the bus.
2. Reinitialize—The processor reinitializes the general-pur-
pose and system registers to their reset values. This is also
not visible on the bus, except as an extended period of inac-
tivity.
3. Jump To BIOS—The processor jumps to the BIOS at address
FFFF_FFF0h, the same entry point used after RESET. This
jump is visible on the far-right side of Figure 5-28 as a burst
code read.