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Signal Descriptions 5-121

18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual

5.2.48 SMIACT (System Management Interrupt Active)

Output

Summary The processor acknowledges the assertion of SMI with the

assertion of SMIACT. The acknowledgment signifies the pro-

cessor’s readiness to enter System Management Mode (SMM)

and begin executing the service routine for that interrupt

mode.

Driven The processor drives SMIACT from after the later of (a) the

last expected BRDY of any in-progress bus cycle, or (b) the

assertion of EWBE with or following the last expected BRDY,

until the return from the SMM interrupt handler via the RSM

instruction.

SMIACT is driven during memory cycles (including cache

writethroughs and writebacks), cache accesses, I/O cycles,

locked cycles, special bus cycles, and interrupt acknowledge

operations in the normal operating modes (Real, Protected,

and Virtual-8086) and in SMM; in the Shutdown, Halt, or Stop

Grant states; or while AHOLD, BOFF, HLDA, or PRDY is

asserted. SMIACT is not driven in the Stop Clock state, or

while RESET is asserted.

Details The memory controller normally uses the assertion of SMIACT

to enable SMM memory, so that the first memory access in

SMM is to the base of the state-save area in the SMM memory

space.

The processor remains in SMM, continuing to assert SMIACT,

until it executes the RSM instruction. For more information

regarding SMM, see the description of SMI on page 5-116, Sec-

tion 6.1.4 on page 6-5, and Section 6.3 on page 6-23.

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