5-120 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
EFLAGS. But the mechanism by which NMI interrupts are dis-
abled and subsequently recognized differs between the
AMD-K5 and Pentium processors.
During SMM, the Pentium processor does not respond to NMI
until the beginning of its response to the first INTR or software
interrupt (INTn) to occur after entering SMM. NMIs can thus
be enabled by using a dummy interrupt. When an INTR or soft-
ware interrupt is recognized, the processor first responds to a
pending NMI interrupt before executing the first instruction of
the INTR handler. By contrast, the AMD-K5 processor recog-
nizes a pending NMI interrupt after returning (via the IRET
instruction) from a prior interrupt.
The same dummy interrupt used on the Pentium processor to
enable NMI recognition during SMM works on the AMD-K5
processor. The only difference is that the AMD-K5 processor
responds to the NMI after the IRET of the dummy interrupt
whereas the Pentium processor responds at the beginning of
the dummy interrupt.
During debugging using the R/S and PRDY protocol, the
debugger can force the processor into SMM but the processor
will not recognize SMI in the Hardware Debug Tool (HDT)
mode.
For further details on the System Management Mode, see
Chapter 6.
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