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AMD K5 User Manual

AMD K5
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3-22 Software Environment and Extensions
AMD-K5 Processor Technical Reference Manual 18524C/0Nov1996
Figure 3-7. Task State Segment (TSS)
31
Interrupt Redirection Bitmap (IRB)
(eight 32-bit locations)
0
I/O Permission Bitmap (IOPB)
(up to 8 Kbyte)
Operating System
Data Structure
Base Address of IOPB
LDT Selector
0000h
0000h
0000h
0000h
0000h
0000h
0000h
GS
FS
DS
SS
CS
ES
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
CR3
EFLAGS
EIP
0000h
0000h
0000h
0000h
SS2
SS1
SS0
Link (Prior TSS Selector)
ESP0
ESP1
ESP2
TSS Limit
from TR
64h
0
T
0000h

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AMD K5 Specifications

General IconGeneral
ManufacturerAMD
ModelK5
Architecturex86
MicroarchitectureK5
Introduction Year1996
Clock Speed75 - 133 MHz
Core Count1
SocketSocket 7
Core steppingSSA/5, 5k86
Voltage3.3V
Transistors4.3 million
L1 Cache8 KB (data) + 16 KB (instruction)
FSB50 MHz to 66 MHz
Process Technology350 nm

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