Noise Reduction 6-41
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
6.7 Noise Reduction
Circuit noise can be minimized by the following design rules:
■ Clock Signal
• Place the processor as close as possible to the clock
source.
• Route the CPUCLK signal on a single PCB layer. Do not
use vias.
• Guard-band the CPUCLK signal with twice the minimum
pitch width to minimize unwanted cross talk.
■ Capacitors
• Place all capacitors as near as possible to the processor.
• Connect the positive sides of all capacitors through vias
directly to the processor power plane.
• Connect the negative sides of all capacitors through vias
to the ground plane.
• Use tantalum 47 µF and 1 µF capacitors.
• Use ceramic capacitors with low equivalent series resis-
tance (ESR) ratings at high frequencies and a minimum
voltage rating of 6 V for all other capacitor values.
• Place some capacitors very near to the processor, prefer-
ably on the inside perimeter of the processor socket.
• Connect bypass capacitors on the top side of the PCB di-
rectly to the processor’s power pins.
■ Multilayer Printed-Circuit Boards
• Use a minimum of four layers—one split power plane,
one ground plane, two routing planes.
■ Regulator Circuit
• Use surface-mounted components placed as near as pos-
sible to the processor.
• Use at least three vias to the +5-V power plane for the in-
put power connection.
• Use at least three vias to the +3-V processor power plane
for the output power connection.
AMD recommends using a split power plane to isolate the pro-
cessor from the rest of the motherboard. This approach
To Next Page
Loading...
Need help?
General
