AMD K5

Signal Descriptions 5-105
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.43 PWT (Page Writethrough)
Output
Summary The processor drives PWT to indicate the operating system’s
specification of writeback or writethrough state for the entire
current page. PWT, together with WB/WT, specifies the data-
cache MESI state of cacheable read misses and write hits.
Driven and Floated The processor drives PWT from the clock in which ADS is
asserted until the last expected BRDY of the bus cycle.
PWT is driven during memory cycles (including cache
writethroughs and writebacks), and locked cycles in the nor-
mal operating modes (Real, Protected, and Virtual-8086), and
in SMM, and when PRDY is asserted. If AHOLD is asserted,
PWT is driven only to complete a bus cycle that had been initi-
ated before AHOLD was asserted. PWT is not driven during
special bus cycles or interrupt acknowledge operations; or in
the Shutdown, Halt or Stop Grant states, except for writebacks
due to inquire cycles; and PWT is never driven during the Stop
Clock state, or while BOFF, HLDA, RESET, or INIT is asserted.
The processor floats PWT one clock after system logic asserts
BOFF and in the same clock that the processor asserts HLDA.
Details As Table 5-14 shows, lines in the modified or exclusive MESI
state are said to be in the writeback state, which corresponds to
PWT = 0. Lines in the shared MESI state are said to be in the
writethrough state, which corresponds to PWT = 1.
System logic can use PWT output, along with its WB/WT input,
to determine how the processor will control internal caching.
Tables 5-17 and 5-18 on page 5-135 show how the state of PWT
and WB/WT determine the MESI state of a line in the data
cache after a cache-line fill or writeback. If WB/WT is Low or
PWT is High during a read miss or a write hit to a shared line,
Table 5-14. PWT, Writeback/Writethrough, and MESI
MESI State Writeback/Writethrough State PWT State
modified writeback 0
exclusive writeback 0
shared writethrough 1
invalid invalid —