AMD K5 User Manual

Bus Cycle Timing 5-181
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Basic Special Bus
Cycle
Figure 5-20 shows a basic special bus cycle, which is defined
during ADS by D/C = 0, M/IO = 0, and W/R = 1 and differenti-
ated by BE7–BE0 and A31–A3. In this example, BE7–BE0
= FBh and A31–A3 = 0, so it is the special cycle the processor
generates after executing a HLT instruction. System logic must
respond with BRDY.
All special bus cycles serialize the pipeline. EWBE is not
checked prior to running special bus cycles (all of which have
W/R =1), so EWBE has no effect on any special bus cycles.
Figure 5-20. Basic Special Bus Cycle (Halt Cycle)
CLK
A31–A3
ADS
BE7–BE0
BRDY
D/C
EWBE
M/IO
W/R
CLK

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm