AMD K5

Built-In Self Test (BIST) 7-5
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
7.2 Built-In Self Test (BIST)
The processor supports the following types of built-in self-test:
■ Normal BIST—A built-in self-test mode typically used to
test system functions after RESET
■ Test Access Port (TAP) BIST—A self-test mode started by the
TAP instruction, RUNBIST
All internal arrays except the TLB are tested in parallel by
hardware. The TLB is tested by microcode. Unlike the Pentium
processor, the AMD-K5 processor does not report parity errors
on IERR for every cache or TLB access. Instead, the AMD-K5
processor fully tests its caches during the BIST. EADS should
not be asserted during a BIST. The processor accesses the phys-
ical tag array during BISTs, and these accesses can conflict
with inquire cycles.
7.2.1 Normal BIST
The normal BIST is invoked if INIT is asserted at the falling
edge of RESET. The BIST runs tests on the internal hardware
that exercise the following resources:
■ Instruction cache:
• Linear tag directory
• Instruction array
• Physical tag directory
■ Data cache:
• Linear tag directory
• Data array
• Physical tag directory
■ Entry-point and instruction-decode PLAs
■ Microcode ROM
■ TLB
The BIST runs a linear feedback shift register (LFSR) signa-
ture test on the microcode ROM in parallel with a March C test
on the instruction cache, data cache, and physical tags. This is
followed by the March C test on the TLB arrays and then an