New Instructions 3-33
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
3.3.5 RDMSR and WRMSR
mnemonic opcode description
RDMSR 0F32 Read model-specific register (MSR)
WRMSR 0F30 Write model-specific register (MSR)
Privilege: CPL = 0
Registers Affected: EAX, ECX, EDX
Flags Affected: none
Exceptions Generated: Real—GP(0) for unimplemented MSR address
Virtual-8086 mode—GP(0)
Protected mode—GP(0) if CPL not = 0
Protected mode—GP(0) for unimplemented MSR address
The RDMSR or WRMSR instructions can be used in Real or Protected mode to access
several 64-bit, model-specific registers (MSRs). These registers are addressed by the
value in ECX, as follows:
■ 00h: Machine-Check Address Register (MCAR). This may contain the physical
address of the last bus cycle for which the BUSCHK or PCHK signal was asserted.
For details, see Section 3.1.1 on page 3-4.
■ 01h: Machine-Check Type Register (MCTR). This contains the cycle definition of
the last bus cycle for which the BUSCHK or PCHK signal was asserted. For
details, see Section 3.1.1 on page 3-4. The processor clears the CHK bit (bit 0) in
MCTR when the register is read with the RDMSR instruction.
■ 10h: Time Stamp Counter (TSC). This contains a time value. The TSC can be ini-
tialized to any value with the WRMSR instruction, and it can be read with either
the RDMSR or RDTSC instruction. For details, see Section 3.2.3 on page 3-27.
■ 82h: Array Access Register (AAR). This contains an array pointer and test data
for testing the processor’s cache and TLB arrays. For details on the AAR, see Sec-
tion 7.4 on page 7-7.
■ 83h: Hardware Configuration Register (HWCR). This contains configuration bits
that control miscellaneous debugging functions. For details, see Section 7.1 on
page 7-3.
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