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AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
A.3.5 Cache Line Ownership
When the processor generates a read hit to a line in its own
ICACHE, the Pentium processor invalidates the ICACHE line
and initiates a DCACHE linefill. However, the AMD-K5 proces-
sor keeps the ICACHE line valid and a non-cacheable, external
read is performed to supply the data.
A.3.6 Write Hit to a Shared Line in the DCACHE
When a write hits a shared line in the DCACHE, the write is
passed through to the external bus. The state of the WB/WT
pin is sampled with the BRDY (or NA) of the write, and if it is
High, the line changes state from shared to exclusive. Subse-
quent writes to the same line change the state of the line from
exclusive to modified and do not go external. Both the AMD-K5
and Pentium processors behave in this manner.
However, if two or more writes to different locations within the
same cache line are queued up in the store buffer, the line is
shared and the WB/WT pin is set High, then the AMD-K5 pro-
cessor correctly allows the first write to reach the bus and the
line transitions to exclusive. The remainder of the writes to
that line do not show up on the external bus. In the Pentium
processor, the first two or more writes go external. The remain-
der hit the line in the exclusive state and do not go external.
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