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7-22 Test and Debug

AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996

7.8.2 Public Instructions

The processor supports all three IEEE-mandatory instructions

(BYPASS, SAMPLE/PRELOAD, EXTEST), three IEEE-

optional instructions (IDCODE, HIGHZ, RUNBIST), and three

instructions unique to the AMD-K5 processor (ALL1, ALL0,

USEHDT). Table 7-6 shows the complete set of public TAP

instructions supported by the processor. In addition, the pro-

cessor implements several private manufacturing test instruc-

tions.

The IEEE standard describes the mandatory and optional

instructions. The ALL1 and ALL0 instructions simply force all

outputs and bidirectionals High or Low. The USEHDT instruc-

tion is described below. Any instruction encodings not shown

in Table 7-6 select the BYPASS instruction.

Table 7-6. Public TAP Instructions

Instruction Encoding Register Description

EXTEST 00000 BSR As defined by the IEEE standard

SAMPLE/

PRELOAD

00001 BSR As defined by the IEEE standard

IDCODE 00010 DIR As defined by the IEEE standard

HIGHZ 00011 BR As defined by the IEEE standard

ALL1 00100 BR Forces all outputs and bidirectionals High

ALL0 00101 BR Forces all outputs and bidirectionals Low

USEHDT 00110 HDTR

Accesses the Hardware Debug Tool (HDT)

See Section 7.9 on page 7-23

RUNBIST 00111 BISTRR As defined by the IEEE standard

BYPASS 11111 BR As defined by the IEEE standard

BYPASS undefined BR

Undefined instruction encodings select the BYPASS

instruction

Notes:

1. Documentation on the Hardware Debug Tool (HDT) is available from AMD under a nondisclosure agreement.

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