AMD K5 User Manual

Bus Cycle Timing 5-159
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
AHOLD-Initiated
Inquire Hit to Shared
or Exclusive Line
Figure 5-10 shows an example similar to Figure 5-9, minus the
address parity error, but this inquire cycle hits either a shared
or exclusive line in the cache, as indicated by the assertion of
HIT and the negation of HITM two clocks after the assertion of
EADS. The processor invalidates the cache line because sys-
tem logic asserts INV with EADS. The processor may drive a
new bus cycle as early as one clock after system logic negates
AHOLD.
Figure 5-10. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line
CLK
A31–A3
ADS
AHOLD
BE7–BE0
BRDY
D/C
D63–D0
EADS
HIT
HITM
INV
M/IO
W/R
CLK
Read Inquire

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm