Memory Management Unit (MMU) 2-27
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
occur out of program order with respect to writes on the bus to
memory.
In a strongly ordered memory-write model, writes to cache and
memory always appear in program order. In a weakly ordered
memory-write model, writes to cache and memory can occur
out of program order (that is, a write to cache can occur before
a prior write to memory). Weakly ordered systems may per-
form better, but they can cause problems in systems with mul-
tiple-caching masters. For example, errors may occur in weakly
ordered systems when a master that is held off the bus contin-
ues writing to exclusive or modified lines in its internal data
cache while another master writes to memory. Nevertheless,
the strongly ordered AMD-K5 processor supports high perfor-
mance without using weakly ordered memory writes by buffer-
ing speculative stores in the store buffer.
2.4.2 Read/Write Reordering
The processor reorders certain types of cacheable read cycles
on the bus ahead of certain types of write cycles. Specifically,
any read that hits in the instruction or data cache is promoted
ahead of a write in the store buffer if the read is not from the
same location to which a write in the store buffer is to be writ-
ten. The reordering allows reads, which dominate the proces-
sor’s use of the bus in Writeback mode, to take precedence
over data writes, which normally occur infrequently. The
EWBE signal has no effect on this reordering of bus cycles.
2.4.3 Segmentation
The instruction cache contains a copy of certain fields in the
current code-segment descriptor. The information is used dur-
ing prefetch for segment translation (logical-to-linear
addresses), thus providing linear-address tags for the instruc-
tion-cache entries. Likewise, the load/store units hold the cur-
rent data-segment descriptors, which are used to generate the
linear address and perform protection checks during data-
cache accesses. The processor can cache segment descriptors
in its data cache.
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