5-96 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.37 NA (Next Address)
Input
Summary The assertion of NA indicates that external memory is pre-
pared for a pipelined cycle.
Sampled The processor samples NA from one clock after ADS until the
first expected BRDY of a bus cycle.
NA is sampled during memory cycles and writethroughs in the
normal operating modes (Real, Protected, and Virtual-8086)
and in SMM. NA is not sampled during writebacks, I/O cycles,
locked cycles, special bus cycles, or interrupt acknowledge
operations; or in the Shutdown, Halt, Stop Grant, or Stop Clock
states; or while BOFF, HLDA, RESET, INIT, or PRDY is
asserted. While AHOLD is asserted, NA is sampled only to
complete a bus cycle already begun before the assertion of
AHOLD.
Details NA is an input that is asserted when external memory is pre-
pared to accept a pipelined cycle. The AMD-K5 processor
drives the pending ADS two clocks after NA is sampled active.
NA does not generate pipelined cycles when LOCK is asserted,
during writeback cycles, or when there are no pending internal
cycles. Furthermore, locked or writeback cycles are not pipe-
lined. KEN and WB/WT are sampled when NA or BRDY is
asserted, whichever comes first.
Refer to the appropriate data sheet for model-specific details
regarding the operation of NA.
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