Debug A-15
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
A.7 Debug
A.7.1 Proprietary Branch Trace Messages
Branch trace messages are different. The AMD-K5 processor
uses the same BE pattern for the special bus cycles as the Pen-
tium processor, but the format of decoding information is
different.
A.7.2 Multiple Debug Breakpoint Matches
Multiple debug breakpoint matches on a single memory access
do not set multiple DR6.B bits on the AMD-K5 processor. The
Pentium processor may set multiple B-bits, regardless of
whether the additional matching debug registers are enabled.
On instructions that do multiple memory accesses, the Pentium
processor sets the DR6.B bits for matching debug registers that
are both enabled and disabled. The AMD-K5 processor only
sets the DR6.B bits for debug registers that are enabled.
A.7.3 Simultaneous Debug Trap and Debug Fault
If a debug trap associated with the completion of an instruc-
tion (single-step trap or load/store breakpoint) occurs at the
same time as a debug fault (instruction breakpoint) on the next
instruction, the Pentium processor merges the two conditions
into a single call to the debug handler, setting both B bits in
the debug status register. The AMD-K5 processor processes the
two conditions serially, setting the appropriate B bits for each
invocation of the handler.
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