AMD K5 User Manual

Memory Management A-11
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
A.4 Memory Management
A.4.1 Speculative TLB Refills
The Pentium processor performs speculative TLB refills
(including setting the accessed bit) for code prefetches. This
may result in the accessed bit being set for a page that is not
actually used. The AMD-K5 processor does not perform specu-
lative TLB refills.
A.4.2 Page Fault Encountered by a Load/Store Type of Instruction
On a read page fault encountered by a load/op/store type of
instruction, the error code reported by a 486 processor indi-
cates a read operation, whereas the Pentium processor
indicates a write operation. The AMD-K5 processor reports the
same error code as the 486 processor.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm