Execution Pipeline 2-5
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Figure 2-2. Pipeline Stage Functions
Fetch
a) Calculate Address
b) Fetch instruction
Predict branch
1 2 3 4 5
Decode 1
a) Merge into byte queue
b) Generate ROPs
Decode 2
a) Merge register tags and immediates
b) Access registers or ROB
Execute
a) Dispatch ROPs to execution units
Calculate operand linear address
1
b) Execute
Arbitrate for result bus
Access operands in data cache
1
Check protection and segment limit
1
Result
Forward to execution units
Write to ROB
Correct branch prediction
Drive write cycle on bus
1
Retire
Write to real-state registers
Forward from ROB
Notes:
1. Load/store instructions only.
2. The Retire stage may occur one or more clocks after completion, but it does not affect throughput.
Fetch Decode 1 Decode 2 Execute Result Retire
2
To Next Page
Loading...
