AMD K5

5-34 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
logic drives KEN with the first BRDY. If system logic negates
KEN, it must return as a single transfer only the bytes speci-
fied on BE7–BE0. If system logic asserts KEN, it must ignore
BE7–BE0 during all transfers of the burst and return all eight
bytes for the starting address on A31–A3. BE7–BE0 does not
change during the four transfers of the burst. (This behavior is
unlike the 486 processor, which drives BE3–BE0 separately for
each transfer of a burst.) System logic must determine the suc-
cessive quadword addresses for each transfer in a burst,
depending on the starting address, as shown in Section 5-4 on
page 5-21.
During single writes, which include cache writethroughs (1-to-
8-byte transfers with CACHE negated) the processor drives the
bits of BE7–BE0 to indicate which of the eight bytes on D63–D0
are valid. During writebacks (32-byte, four-transfer bursts with
CACHE asserted) the processor drives all bits of BE7–BE0 Low
to indicate that all eight bytes on D63–D0 are valid. Write-
backs are addressed by A31–A3 but they are always aligned to
32-byte boundaries, so A4–A3 are always 0.
The processor differentiates special bus cycles using a combi-
nation of BE7–BE0, the cycle definition (D/C, M/IO, and W/R)
outputs, and A31–A3. The values on the cycle definition signals
are the same for all special cycles; only BE7–BE0 and A31–A3
differentiate among those cycles. Table 5-6 shows the relation-
Table 5-5. Relation Of BE7–BE0 To Other Signals
Byte Enable
Output
Effective Address Bits
1
Byte On Data
Bus
Data Parity Bit
A2 A1 A0
BE7
111D63–D56 D7
BE6
1 1 0 D55–D48 D6
BE5
1 0 1 D47–D40 D5
BE4
1 0 0 D39–D32 D4
BE3
0 1 1 D31–D24 D3
BE2
0 1 0 D23–D16 D2
BE1
0 0 1 D15–D8 D1
BE0
000 D7–D0 D0
Notes:
1. BE7–BE0 expand on the function of A2–A0 by allowing the processor to address any or all
eight bytes addressed by A31–A3.