AMD K5

Signal Descriptions 5-53
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.17 D/C (Data or Code)
Output
Summary The processor drives D/C to indicate whether it is accessing
data or executable code on the bus. The signal is driven at the
same time as the other two cycle definition signals: M/IO and
W/R. A specific encoding of D/C, M/IO, and W/R identifies one
of several special bus cycles.
Driven and Floated The processor drives D/C from ADS until the last expected
BRDY of the bus cycle.
D/C is driven with the other cycle definition outputs (M/IO and
W/R) and with the BE7–BE0 byte-enable outputs during mem-
ory cycles (including cache writethroughs and writebacks), I/O
cycles, locked cycles, special bus cycles, and interrupt
acknowledge operations in the normal operating modes (Real,
Protected, and Virtual-8086) and in SMM, or while PRDY is
asserted. While AHOLD is asserted, D/C is driven only to com-
plete a bus cycle that had been initiated before AHOLD was
asserted, or for inquire cycle writebacks. During the Shut-
down, Halt, and Stop Grant states, D/C is driven only for
inquire cycle writebacks. D/C is not driven during the Stop
Clock state, or while BOFF, HLDA, RESET, or INIT is asserted.
The processor floats D/C one clock after system logic asserts
BOFF and in the same clock that the processor asserts HLDA.
Details The processor drives D/C according to whether the access is
initiated by the processor’s prefetch or branch logic (indicating
a code access) or its load/store logic (indicating a data access).
In the AMD-K5 processor, code accesses can be done specula-
tively, but data accesses are not. Only data (not code) can be
read from the I/O address space, because the cycle definition
for an I/O code read (D/C = 0, M/IO = 0, W/R = 0) defines an
interrupt acknowledge cycle.
Before the processor fetches an instruction or reads or writes a
data operand, it checks the descriptor for the segment contain-
ing the code or data to verify that such action is allowed. The
execute (E) bit in the segment descriptor distinguishes
between data and code segments. A general-protection excep-
tion is generated if the E bit does not match the D/C type.