AMD K5 User Manual

5-54 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
During special bus cycles, the processor drives D/C = 0, M/IO =
0, and W/R = 1. The cycles are then differentiated by BE7–BE0
and A31–A3.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm