AMD K5 User Manual

Signal Descriptions 5-131
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.54 TRST (Test Reset)
Input
Summary The assertion of TRST initializes the Test Access Port (TAP) by
resetting its state machine.
Sampled TRST is an asynchronous input. Unlike other asynchronous
inputs, no synchronous setup and hold time are specified for
TRST. TRST has an internal pullup resistor.
TRST is always sampled, except while RESET or INIT is
asserted.
Details When TRST is asserted, the TAP controller enters its test-
reset-logic state, regardless of the controller state. This action
is the same as that achieved by holding TMS asserted for five
or more clocks. The assertion of TRST is unnecessary at
RESET because the processor performs the TAP reset auto-
matically at that point.
See the IEEE Standard Test Access Port and Boundary-Scan
Architecture (IEEE 1149.1) specification for a description of
how the TAP signals and instructions are used for testing.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm