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7-16 Test and Debug

AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996

7.5 Debug Registers

The processor implements the standard debug functions and

registers—DR7–DR6 and DR3–DR0 (often called DR7–DR0)—

that are available on the 486 processor, plus an I/O breakpoint

extension.

7.5.1 Standard Debug Functions

The debug functions make the processor’s state visible to

debug software through four debug registers (DR3–DR0) that

are accessed by MOV instructions. Accesses to memory

addresses can be set as breakpoints in the instruction flow by

invoking one of two debug exceptions (interrupt vectors 1 or 3)

during instruction or data accesses to the addresses. The debug

functions eliminate the need to embed breakpoints in code and

allow debugging of ROM as well as RAM.

For details on the standard 486 debug functions and registers,

see the AMD documentation on the Am486

processor or other

commercial x86 literature.

7.5.2 I/O Breakpoint Extension

The processor supports an I/O breakpoint extension for break-

points on I/O reads and writes. This function is enabled by set-

ting bit 3 of CR4, as described in Section 3.1 on page 3-2. When

enabled, the I/O breakpoint function is invoked by the follow-

ing:

■ Entering the I/O port number as a breakpoint address (zero-

extended to 32 bits) in one of the breakpoint registers,

DR3–DR0

■ Entering the bit pattern, 10b, in the corresponding 2-bit

R/W field in DR7

All data breakpoints on the AMD-K5 processor are precise,

including those encountered in repeated string operations,

which trap after completing the iteration on which the break-

point match occurs.

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